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PE3282A
1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis
Applications * Cellular handsets * Cellular base stations * Spread-spectrum radio * Cordless phones * Pagers Description
The PE3282A is a dual fractional-N phase-locked loop integrated circuit designed for frequency synthesis and fabricated on Peregrine's patented UTSi(R) CMOS process. Each PLL includes a prescaler, phase detector, charge pump and on-board fractional spur compensation. The 32/33 RF prescaler (PLL1) operates up to 1.1 GHz and the 16/17 IF prescaler (PLL2) operates up to 510 MHz. The PE3282A provides fractional-N division with power-of-two denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase-noise floor than integer PLLs.
Figure 1. PE3282A Block Diagram
fin1 fin1 Gnd fr Gnd 6 5 7 8 9 Ref Amp 9-Bit Reference Divider 21-Bit Serial Control Interface 9-Bit Reference Divider Gnd fin2 fin2 14 16 15 16/17 Prescaler 18-Bit Fractional-N Main Divider Fractional Spur Compensation Phase Detector Charge Pump 32/33 Prescaler 19-Bit Fractional-N Main Divider
Features * Modulo-32 fractional-N main counters * On-board fractional spur compensation: no tuning required, stable over temperature * Improved phase noise compared to integer-N architectures * Low power--8.5 mA at 3 V * Integrated 1.1 GHz / 32/33 prescaler * Integrated 510 MHz / 16/17 prescaler
Fractional Spur Compensation
1 2 3 4
VDD VDD CP1 Gnd foLD Gnd CP2 VDD VDD
Clock 11 Data LE 12 13
Multiplexer
10 17
Phase Detector
Charge Pump
18 19 20
Peregrine Semiconductor Corporation(R)
6175 Nancy Ridge Drive, San Diego, CA 92121 Tel (619) 455-0660 Fax (619) 455-0770 http://www.peregrine-semi.com
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Figure 2. Pin Configuration TSSOP (JEDEC MO-153-AC)
VDD VDD CP1 Gnd fin1 fin1 Gnd fr Gnd foLD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VDD CP2 Gnd fin2 fin2 Gnd LE Data Clock
Table 1. PE3282A Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name VDD
VDD
Type (Note 1) (Note 1) Output
Description Power supply voltage input. Input may range from 2.7 V to 3.6 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Same as pin 1. Internal charge-pump output for PLL1. For connection to a loop filter for driving the input of an external VCO. Ground. Prescaler input from the PLL1 (RF) VCO. 1.1 GHz max frequency. 1.1 GHz prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. Ground. Reference frequency input. Ground. Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 10, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. A pull-down resistor is recommended. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. A pull-down resistor is recommended. Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). A pull-down resistor is recommended. Ground. 510 MHz prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity. Prescaler input from the PLL2 (IF) VCO. 510 MHz max frequency. Ground. Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Same as pin 1. Same as pin 1.
CP1 Gnd fin1 fin1 Gnd fr Gnd foLD Clock Data
Input Input
Input
Output Input Input
13 14 15 16 17 18 19 20
LE Gnd fin2 fin2 Gnd CP2 VDD VDD
Input
Input Input Output (Note 1) (Note 1)
Note 1: VDD pins 1, 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
2
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Ratings and Operating Ranges
Table 2. Absolute Maximum Ratings
Symbol VDD VI II Tstg Parameter/Conditions Supply voltage Voltage on any input DC into any input or output Storage temperature range Min -0.3 -0.3 -10 -65 Max 4.0 VDD + 0.3 +10 150 Unit V V mA C
Table 3. Operating Ranges
Symbol VDD TA Parameter/Conditions Supply voltage Operating ambient temperature range Min 2.7 -40 Max 3.6 85 Unit V C
Table 4. ESD Ratings
Symbol VESD Parameter/Conditions ESD Voltage, Human body model (Note 1) Min 2000 Max Unit V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-STD-883, M3015 C2; 2KV.
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4.
Latch-up Avoidance
Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
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PE3282A
Table 5. DC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless specified Symbol IDD Parameter Operational supply current; PLL1 (RF) enabled PLL2 (IF) enabled PLL1 and PLL2 enabled Total standby current Conditions VDD = 2.7 to 3.6 V 5.5 3.0 8.5 25 mA mA mA mA Min Typ Max Unit
Istby
Digital inputs: Clock, Data, LE VIH VIL IIH IIL High level input voltage Low level input voltage High level input current Low level input current VDD = 2.7 to 3.6 V VDD = 2.7 to 3.6 V VIH = VDD = 3.6 V VIL = 0, VDD = 3.6 V -1 -1 0.7 x VDD 0.3 x VDD +1 +1 V V mA mA
Reference Divider input: fr IIHR IILR Input current Input current VIH = VDD = 3.6 V VIL = 0, VDD = 3.6 V -100 +100 mA mA
Digital output: foLD VOLD VOHD Output voltage LOW Output voltage HIGH Iout = 1 mA Iout = -1 mA VDD - 0.4 0.4 V V
Charge Pump outputs: CP1, CP2 ICP - Source ICP - Sink ICPL ICP - Source vs. ICP - Sink ICP vs. TA Output current vs. temperature ICP vs. VCP Output current magnitude variation vs. voltage Drive current Leakage current Sink vs. source mismatch VCP = VDD/2, TA = 25 C 0.5 < VCP < VDD - 0.5 V VCP = VDD/2, TA = 25 C VCP = VDD/2 + 85 C VCP = VDD/2 - 40 C 0.5 < VCP < VDD - 0.5 V, TA = 25 C -18 +8 20 -5 -70 70 5 20 mA mA nA % % % %
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Table 6. AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless specified Symbol Parameter Conditions Min Max Unit
Serial Control Interface (see Figure 3) fClock tClockH tClockL tDSU tDHLD tLEW tCLE tLEC tData Out Serial data clock frequency Serial clock HIGH time Serial clock LOW time Data set-up time to Clock rising edge Data hold time after Clock rising edge LE pulse width Clock falling edge to LE rising edge LE falling edge to Clock rising edge Data Out delay after Clock falling edge (foLD pin) CL = 50 pf 50 50 50 10 50 50 50 90 10 MHz ns ns ns ns ns ns ns ns
Main Divider (Including Prescaler) fin1 fin2 Pfin1 Pfin2 fc Operating frequency Operating frequency Input level range Input level range Comparison frequency External AC coupling External AC coupling 100 45 -10 -10 1,100 510 5 5 10 MHz MHz dBm dBm MHz
Reference Divider fr Vfr Operating frequency Input sensitivity External AC coupling (Note 1) 0.5 50 MHz VP-P
Note 1: CMOS logic levels may be used if DC coupled.
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PE3282A Functional Description
The Functional Block Diagram in Figure 2 shows a 21bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase detector, and an internal charge pump with on-chip fractional spur compensation. Each fractional-N main counter chain includes an internal dual modulus prescaler, supporting counters and a fractional accumulator. Serial input data is clocked on the rising edge of Clock, MSB first. The last two bits are the address bits that determine the register address. Data is transferred into the counters as shown in Table 7, PE3282A Register Set. If the foLD pin is configured as data out, then the contents of shift register bit S20 are clocked on the falling edge of Clock onto the foLD pin. This feature allows the PE3282A and compatible devices to be connected in a daisy-chain configuration. The PLL1 (RF) VCO frequency fin1 is related to the reference frequency fr by the following equation: fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1) (1) Note that A1 must be less than M1. Also, fin1 must be greater than or equal to 1024 x (fr/R1) to obtain contiguous channels. The PLL2 (IF) VCO frequency fin2 is related to the reference frequency fr by the following equation: fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2) (2) Note that A2 must be less than M2. Also, fin2 must be greater than or equal to 256 x (fr/R2) to obtain contiguous channels. F1 sets PLL1 fractionality. If F1 is an even number, PE3282A automatically reduces the fraction. For example, if F1 = 12, then the fraction 12/32 is automatically reduced to 3/8. In this way, fractional denominators of 2, 4, 8, 16 and 32 are available. F2 sets the fractionality for PLL2 in the same manner.
Figure 3. PE3282A Functional Block Diagram PLL1 (RF)
A1 5 A1 Counter 0 A1 31 M1 9 M1 Counter 3 M1 511 R1 Counter 3 R1 511 R1 9 Clock Data LE
Prescaler Control Logic F1 5 F1 Counter 0 F1 31 Phase Detector C11 C12 foLD Data Out Multiplexer C21 Phase Detector C22 Charge Pump Fractional Compensation CP2 C13 C14 C23 C24 foLD
fin1 fin1 fr
Prescaler 32/33
Fractional Compensation Charge Pump CP1
Serial Control Interface
PLL2 (IF)
fin2 fin2 Prescaler 16/17
R2
9 R2 Counter 3 R2 511 M2 Counter 3 M2 511 M2 9 A2 Counter 0 A2 15 A2 4
F2 Counter 0 F2 31 F2 5 Prescaler Control Logic
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Table 7. PE3282A Register Set
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Test PLL2 Synthesizer control Reserved 0 C24 C23 C22 C21 C20
PLL2 Reference counter R2 divide ratio R28 R27 R26 R25 R24 R23 R22 R21 R20
Address 0 0
PLL2 Main counter M2 divide ratio Res.
PLL2 Swallow counter A2 divide ratio A22 A21
PLL2 Fractional counter F2 numerator value A20 F24 F23 F22 F21 F20
Address
M28 M27 M26 M25 M24 M23 M22 M21 M20 A23 PLL1 Synthesizer control Reserved C14 C13 C12 C11 C10
0
1
PLL1 Reference counter R1 divide ratio R18 R17 R16 R15 R14 R13 R12 R11 R10
Address 1 0
PLL1 Main counter M1 divide ratio
PLL1 Swallow counter A1 divide ratio A13 A12 A11
PLL1 Fractional counter F1 numerator value F13 F12 F11 F10
Address 1 1
M18 M17 M16 M15 M14 M13 M12 M11 M10 A14
A10 F14
MSB (first in)
(last in) LSB
Figure 4. Serial Control Interface Data Timing Diagram
Data
Clock
LE tDSU tDHLD tClockH tClockL tLEW tLEC tCLE tData Out Data Out (foLD pin)
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PE3282A
Programmable Divide Values (R1, R2, F1, F2, A1, A2, M1, M2)
Data is clocked into the 21-bit shift register, MSB first. When LE is asserted HIGH, data is latched into the registers addressed by the last two bits shifted into the 21-bit shift register, according to Table 7. For example, to program the PLL1 (RF) swallow counter, A1, the last two bits shifted into the register (S0 , S1) would be (1, 1). The 5bit A1 counter would then be programmed according to Table 8. For normal operation, S16 of address (0, 0) (the Test bit) must be programmed to 0 even if PLL2 (IF) is not used.
Table 8. PE3282A Counter Programming Example
Divide Value MSB S11 A14 0 1 2 * 31 0 0 0 * 1 S10 A13 0 0 0 * 1 S9 A12 0 0 0 * 1 S8 A11 0 0 1 * 1 LSB S7 A10 0 1 0 * 1 Address S1 1 1 1 1 1 1 S0 1 1 1 1 1 1
Programmable Modes
Several modes of operation can be programmed with bits C10 - C14 and C20 - C24 , including the phase detector polarity, charge pump high impedance, output of the foLD pin and power-down modes. The truth table for the programmable modes is shown in Table 9. The truth table for the foLD output is shown in Table 10.
Table 9. PE3282A Programmable Modes
S15 C24 see Table 10 S14 C23 see Table 10 S13 C22 0 = PLL2 CP normal 1 = PLL2 CP High Z S12 C21 (Note 2) 0 = PLL2 Phase Detector inverted 1 = PLL2 Phase Detector normal S11 C20 (Note 1) 0 = PLL2 on 1 = PLL2 off S1 0 S0 0
C14 see Table 10
C13 see Table 10
C12 0 = PLL1 CP normal 1 = PLL1 CP High Z
C11 (Note 2) 0 = PLL1 Phase Detector inverted 1 = PLL1 Phase Detector normal
C10 (Note 1) 0 = PLL1 on 1 = PLL1 off
1
0
Note 1: The PLL1 power-down mode disables all of PLL1's components except the R1 counter and the reference frequency input buffer, with CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times. Note 2: The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 4. This relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Figure 5. VCO Characteristics
* When VCO1 (RF) slope is positive like (1), C11 should be set HIGH. * When VCO1 (RF) slope is negative like (2), C11 should be set LOW. * When VCO2 (IF) slope is positive like (1), C21 should be set HIGH. * When VCO2 (IF) slope is negative like (2), C21 should be set LOW.
VCO Output Frequency (1) Positive Slope VCO
(2) Negative Slope VCO VCO Input Voltage
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Table 10. foLD Programming Truth Table
X = don't care condition foLD Output State Disabled (Note 1) PLL1 Lock detect (Note 2) (LD1) PLL2 Lock detect (Note 2) (LD2) PLL1/PLL2 Lock detect (Note 2) PLL1 Reference divider output (fc1) PLL2 Reference divider output (fc2) PLL1 Programmable divider output (fp1) PLL2 Programmable divider output (fp2) Serial data out Reserved Reserved Counter reset (Note 3) C14 (PLL1 fo) 0 0 0 0 1 0 1 0 1 1 1 1 C13 (PLL1 LD) 0 1 0 1 X X X X 0 0 1 1 C24 (PLL2 fo) 0 0 0 0 0 1 0 1 1 1 1 1 C23 (PLL2 LD) 0 0 1 1 0 0 1 1 0 1 0 1
Note 1: When the foLD is disabled the output is a CMOS LOW. Note 2: Lock detect indicates when the VCO frequency is in "lock" When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin . will be HIGH, with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH, with narrow pulses LOW. When PLL1/PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW, only when both PLL1 and PLL2 are in lock. Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon powering up.
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PE3282A
Phase Comparator Characteristics
PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1 directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged. PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2 directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged.
Figure 6. Phase Comparator Timing Diagram
fc1(2) (Note 1)
fp1(2) (Note 1)
LD1(2) (Note 1)
UP1(2)
DOWN1(2) fc leads fp fc = fp fc lags fp fc lags fp fc lags fp
Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 10.
10
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Figure 7. Typical Application Example
VDD VDD .01 F 220 pF 220 pF .01 F .01 F VDD VDD 220 pF 220 pF .01 F
VDD PLL1 (RF) OUT 220 pF VCO (Note 1) R2 VDD CP1
VDD VDD CP2 Gnd R3 fin2 fin2 Gnd 51K LE Data 51K Clock 51K 1000 pF (Note 2) R4 1000 pF VCO (Note 1)
PLL2 (IF) OUT
C2
C1
R1 (Note 2)
Gnd fin1 220 pF fin1 Gnd fr Gnd
C3
C4
Reference Input
1000 pF (Note 3)
foLD Output
foLD
From Controller
Table 11. PLL1 (RF)
Operating Conditions fout = 948.075 MHz fref = 14.4 MHz fcomp = 800 kHz Fractionality = 32 Step Size = 25 kHz Loop Filter Values (Note 4) R2 = 30 k ohm C2 =.0043 F C1 = 900 pF
Table 12. PLL2 (IF)
Operating Conditions fout = 130.45 MHz fref = 14.4 MHZ fcomp = 800 kHz Fractionality = 16 Step Size = 50 kHz Loop Filter Values (Note 4) R4 = 7.1 k ohm C4 =.027 F C3 =.0056 F
n = 3.0 kHz
Phase Margin = 45 N = 1,185 + 3/32 (M = 37, A = 1, F = 3) KVCO = 13 MHz/V Kpd = 70 A/2 1/4 rad
n = 2.0 kHz
Phase Margin = 45 N = 163 + 1/16 (M = 10, A = 3, F = 2) KVCO = 5 MHz/V Kpd = 70 A/2 1/4 rad
Note 1: VCO output assumed to be AC coupled. Note 2: R1 and R3 are chosen to set the input drive to pins fin1 and fin2. R1 and R3 also allow a larger proportion of the VCO output to be delivered to the load and attenuate reflected energy from the PLL inputs. Note 3: The fr input may be DC coupled if driven by an appropriate CMOS level signal. A 50 ohm terminating resistor can be used when driving the fr pin from an external 50 ohm signal source. Note 4: The unity gain bandwidth is recommended to be less than or equal to 10 percent of the step size.
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Mechanical Information
Figure 8. Package Dimensions: TSSOP (JEDEC MO-153-AC)
1.20 MAX Seated Height 0.05 MIN Stand Off
6.50 0.10 20 11
0.60 0.15
Index
6.40 0.30 4.40 0.10
(dimensions in millimeters)
1
10
0.65 TYP
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Ordering Information
Peregrine Semiconductor Corp. standard products are often available in several packages and performance ranges. Part numbers for ordering the various configurations are defined as follows:
Table 13.Valid ordering number combinations for PE3282A:
Order Code 3282-11 3282-12 3282-00 Part Marking PE3282A PE3282A PE3282A-EK Package 20 lead TSSOP 20 lead TSSOP Evaluation Kit Temperature -40 to 85 C -40 to 85 C -40 to 85 C Shipping Method Tube 74 Units/Tube Tape and Reel 2500 Units/Reel 1/Box
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Peregrine Semiconductor Corporation(R)
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Sales Offices
United States
Peregrine Semiconductor Corporation. 6175 Nancy Ridge Drive San Diego, CA 92121 Tel (619) 455-0660 Fax (619) 455-0770
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following US patents: 5,416,043; 5,600,169; 5,572,040; 5,492,857; 5,663,570; 5,596,205; 5,610,790. Other patents may be pending or applied for.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. The information in this data shee is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
UTSi, the Peregrine logotype, Microcommunicator, SEL Safe, and Peregrine Semiconductor Corporation are registered trademarks of Peregrine Semiconductor Corporation. PE3282A and all PE product prefixes are trademarks of Peregrine Semiconductor Corporation. Copyright (c) 1998 Peregrine Semiconductor Corporation. All rights reserved.
Peregrine Semiconductor Corporation(R)
6175 Nancy Ridge Drive, San Diego, CA 92121 Tel (619) 455-0660 Fax (619) 455-0770 http://www.peregrine-semi.com
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